TSMC Reportedly Developing Packaging Technology Similar to Intel EMIB, Stock Price Surges 8% Intraday

TSMC is developing an advanced chip packaging technology similar to Intel’s EMIB. Internally, this project is referred to as “EMIB-like,” and discussions have already begun with some clients.

On July 30, reports cited two sources indicating that TSMC engineers have been advancing this project internally, aiming to provide a packaging solution with features comparable to Intel’s EMIB.

Chip packaging is the final stage in semiconductor manufacturing, assembling different silicon dies into a single unit and wiring them, enabling them to function as a whole.

TSMC currently dominates the AI chip packaging market with its CoWoS technology, but the company has recently expanded its packaging capabilities by launching a CoWoS glass substrate development plan and establishing a CoPoS pilot production line, among other measures.

The exposure of the EMIB-like project further enriches TSMC’s portfolio of advanced packaging technologies and reflects how industry competition is extending from process nodes to packaging. Following the news, TSMC shares opened up more than 3% in the U.S. on Thursday, continued to rise, and ended up 7.6% higher.

What Is “EMIB-like”?

Chip packaging is the final stage of chip manufacturing.

Intel’s EMIB is one of the core technologies the company uses to meet advanced packaging demands.

This technology is officially called “Embedded Multi-die Interconnect Bridge.” Traditional 2.5D packaging requires placing a large silicon interposer beneath the chip to make connections, while EMIB embeds micro silicon bridges only where connections are needed—like building a small bridge between two plots of land instead of paving an entire road.

Recently, the technology has made significant progress. The EMIB-T version’s yield rate has risen to 98% and has secured orders from major firms including NVIDIA, Google, and OpenAI.

CoWoS Is Not the Endpoint

TSMC has long used CoWoS technology to support advanced AI chip packaging requirements.

However, even as the company rapidly expands CoWoS production capacity, the industry still expects chip supply shortages to continue beyond 2027.

Nomura expects TSMC’s CoWoS capacity target to reach 2 million wafers by 2027, with NVIDIA accounting for about 55% of that total.

To address capacity bottlenecks, TSMC previously announced a CoWoS glass substrate development plan and set up a CoPoS pilot line in Tainan, China, with mass production expected in the second half of 2028. NVIDIA’s Feynman architecture GPUs will be the first products based on this.

From an industry perspective, Intel is solidifying its differentiated advantage in advanced packaging through EMIB, while Samsung is accelerating its deployment of new-generation solutions like glass substrates. By adding EMIB-like to its CoWoS base, TSMC demonstrates that packaging is now a new battleground for major wafer fabs competing for technological leadership.